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| an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. advance information for pre-production products; subject to change without notice. ads1278-sp sbas937 ? september 2018 ads1278-sp radiation hardened 8-ch simultaneous-sampling 24-bit analog-to-digital converter 1 1 features 1 ? radiation hardened ? tid 75 krad(si) ? tid radiation lot acceptance test (rlat) tbd ? single event latchup (sel) immune to let 68 mev-cm 2 /mg @ 125 c ? simultaneously samples eight channels ? up to 128-ksps data rate ? ac performance: ? 63-khz bandwidth ? 111-db snr (high-resolution mode) ? ? 108-db thd ? dc accuracy: ? 0.8- v/ c offset drift ? 1.3-ppm/ c gain drift ? selectable operating modes: ? high-speed: 128 ksps, 106-db snr ? high-resolution: 52 ksps, 111-db snr ? low-power: 52 ksps, 31 mw/ch ? low-speed: 10 ksps, 7 mw/ch ? linear phase digital filter ? spi ? or frame-sync serial interface ? low sampling aperture error ? modulator output option (digital filter bypass) ? analog supply: 5 v ? digital core: 1.8 v ? i/o supply: 1.8 v to 3.3 v 2 applications ? space systems (satellite, shuttles, stations) ? satellite temperature and position sensing ? orbital observation systems ? precision and scientific applications ? high-accuracy instrumentation 3 description the ads1278-sp (octal) is a 24-bit, delta-sigma ( ) analog-to-digital converter (adc) with data rates up to 128k samples per second (sps), allowing simultaneous sampling of eight channels. traditionally, industrial delta-sigma adcs offering good drift performance use digital filters with large passband droop. as a result, they have limited signal bandwidth and are mostly suited for dc measurements. high-resolution adcs in audio applications offer larger usable bandwidths, but the offset and drift specifications are significantly weaker than respective industrial counterparts. the ads1278-sp combines these types of converters, allowing high-precision industrial measurement with excellent dc and ac specifications. the high-order, chopper-stabilized modulator achieves very low drift with low in-band noise. the onboard decimation filter suppresses modulator and signal out-of-band noise. these adcs provide a usable signal bandwidth up to 90% of the nyquist rate with less than 0.005 db of ripple. device information (1) part number grade package ads1278mhfq-mls flight grade 75 krad(si); ? 55 c to 125 c 84-pin hfq ads1278whfq-mls flight grade 75 krad(si); ? 55 c to 115 c ads1278hfq/em engineering samples (2) ads1278evm-cval ceramic evaluation board evm (1) for all available packages, see the orderable addendum at the end of the data sheet. (2) these units are intended for engineering evaluation only. they are processed to a noncompliant flow. these units are not suitable for qualification, production, radiation testing or flight use. parts are not warranted for performance over the full mil specified temperature range of ? 55 c to 125 c or operating life. simplified schematic advance information ads1278-sp vrefp vrefn avdd dvdd test[1:0] format[2:0] clk sync pwdn[8:1] clkdiv control logic spi and frame- sync interface iovdd dgnd agnd drdy/fsync sclkdout[8:1] din input2 input1input4 input3input6 input5input8 input7 ds ds ds ds ds ds ds ds mode[1:0] eight digital filters tools & software technical documents ordernow productfolder support &community
2 ads1278-sp sbas937 ? september 2018 www.ti.com product folder links: ads1278-sp submit documentation feedback copyright ? 2018, texas instruments incorporated table of contents 1 features .................................................................. 1 2 applications ........................................................... 1 3 description ............................................................. 1 4 revision history ..................................................... 2 5 description (continued) ......................................... 3 6 pin configuration and functions ......................... 3 7 specifications ......................................................... 6 7.1 absolute maximum ratings ...................................... 6 7.2 esd ratings .............................................................. 6 7.3 recommended operating conditions ....................... 6 7.4 thermal information .................................................. 6 7.5 electrical characteristics ........................................... 7 7.6 timing requirements: spi format ............................ 9 7.7 timing requirements: frame-sync format ............ 11 7.8 quality conformance inspection ............................. 11 7.9 typical characteristics ............................................ 13 8 detailed description ............................................ 22 8.1 overview ................................................................. 22 8.2 functional block diagram ....................................... 23 8.3 feature description ................................................. 23 8.4 device functional modes ........................................ 45 9 application and implementation ........................ 46 9.1 application information ............................................ 46 9.2 typical application .................................................. 46 10 power supply recommendations ..................... 49 11 layout ................................................................... 50 11.1 layout guidelines ................................................. 50 11.2 layout example .................................................... 51 12 device and documentation support ................. 52 12.1 receiving notification of documentation updates 52 12.2 community resources .......................................... 52 12.3 trademarks ........................................................... 52 12.4 electrostatic discharge caution ............................ 52 12.5 glossary ................................................................ 52 13 mechanical, packaging, and orderable information ........................................................... 53 4 revision history note: page numbers for previous revisions may differ from page numbers in the current version. date revision notes september 2018 * initial release. advance information 3 ads1278-sp www.ti.com sbas937 ? september 2018 product folder links: ads1278-sp submit documentation feedback copyright ? 2018, texas instruments incorporated 5 description (continued) four operating modes allow for optimization of speed, resolution, and power. all operations are controlled directly by pins; there are no registers to program. the device is fully specified over the extended temperature range of ? 55 c to 125 c and is available in an 84-pin hfq package. 6 pin configuration and functions hfq package 84-pin cfp top view advance information 20 22 21 23 24 25 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 2627 28 29 3031 3233 34 35 36 3738 39 40 4142 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 84 8382 81 80 7978 76 7574 73 72 71 70 69 68 6766 6564 77 4 ads1278-sp sbas937 ? september 2018 www.ti.com product folder links: ads1278-sp submit documentation feedback copyright ? 2018, texas instruments incorporated pin functions pin i/o description name no. agnd analog ground analog ground; connect to dgnd using a single plane. ainp1 analog input ainp[8:1] positive analog input, channels 8 through 1. ainp2 analog input ainp3 analog input ainp4 analog input ainp5 analog input ainp6 analog input ainp7 analog input ainp8 analog input ainn1 analog input ainn[8:1] negative analog input, channels 8 through 1. ainn2 analog input ainn3 analog input ainn4 analog input ainn5 analog input ainn6 analog input ainn7 analog input ainn8 analog input avdd analog power supply analog power supply (4.75 v to 5.25 v). vcom analog output avdd / 2 unbuffered voltage output. vrefn analog input negative reference input. vrefp analog input positive reference input. clk digital input master clock input. clkdiv digital input clk input divider control: 1 = 32.768 mhz (high-speed mode only) / 27 mhz 0 = 13.5 mhz (low-power) / 5.4 mhz (low-speed) dgnd digital ground digital ground power supply. din digital input daisy-chain data input. dout1 digital output dout1 is tdm data output (tdm mode). dout2 digital output dout[8:1] data output for channels 8 through 1. dout3 digital output dout4 digital output dout5 digital output dout6 digital output dout7 digital output dout8 digital output drdy/ fsync digital input/output frame-sync protocol: frame clock input; spi protocol: data ready output. dvdd digital power supply digital core power supply (+1.65 v to +1.95 v). format0 digital input format[2:0] selects frame-sync/spi protocol, tdm/discrete data outputs, fixed/dynamic position tdm data, and modulator mode/normal operating mode. format1 digital input format2 digital input iovdd digital power supply i/o power supply (+1.65 v to +3.6 v). mode0 digital input mode[1:0] selects high-speed, high-resolution, low-power, or low-speed mode operation. mode1 digital input advance information 5 ads1278-sp www.ti.com sbas937 ? september 2018 product folder links: ads1278-sp submit documentation feedback copyright ? 2018, texas instruments incorporated pin functions (continued) pin i/o description name no. pwdn1 digital input pwdn[8:1] power-down control for channels 8 through 1. pwdn2 digital input pwdn3 digital input pwdn4 digital input pwdn5 digital input pwdn6 digital input pwdn7 digital input pwdn8 digital input sclk digital input/output serial clock input, modulator clock output. sync digital input synchronize input (all channels). test0 digital input test[1:0] test mode select: 00 = normal operation 11 = test mode 01 = do not use 10 = do not use test1 digital input advance information 6 ads1278-sp sbas937 ? september 2018 www.ti.com product folder links: ads1278-sp submit documentation feedback copyright ? 2018, texas instruments incorporated (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions . exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 7 specifications 7.1 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) (1) min max unit avdd to agnd ? 0.3 6 v agnd to dgnd ? 0.3 3.6 v dvdd, iovdd to dgnd ? 0.3 0.3 v input current momentary 100 ma continuous 10 analog input to agnd ? 0.3 avdd + 0.3 v digital input or output to dgnd ? 0.3 dvdd + 0.3 v junction temperature hfq and hkp packages ? 55 217 c d package ? 55 175 storage temperature, t stg ? 60 150 c (1) jedec document jep155 states that 500-v hbm allows safe manufacturing with a standard esd control process. (2) jedec document jep157 states that 250-v cdm allows safe manufacturing with a standard esd control process. 7.2 esd ratings value unit v (esd) electrostatic discharge human-body model (hbm), per ansi/esda/jedec js-001 (1) tbd v charged-device model (cdm), per jedec specification jesd22- c101 (2) tbd 7.3 recommended operating conditions over operating free-air temperature range (unless otherwise noted) min nom max unit t j operating junction temperature ads1278mhfq-mls ? 55 125 c ads1278whfq-mls ? 55 115 (1) for more information about traditional and new thermal metrics, see the semiconductor and ic package thermal metrics application report. 7.4 thermal information thermal metric (1) ads1278-sp unit hfq (cfp) 84 pins r ja junction-to-ambient thermal resistance 23.7 c/w r jc(top) junction-to-case (top) thermal resistance 9.6 c/w r jb junction-to-board thermal resistance 11.5 c/w jt junction-to-top characterization parameter 3.0 c/w jb junction-to-board characterization parameter 10.9 c/w r jc(bot) junction-to-case (bottom) thermal resistance 7.7 c/w advance information 7 ads1278-sp www.ti.com sbas937 ? september 2018 product folder links: ads1278-sp submit documentation feedback copyright ? 2018, texas instruments incorporated (1) for subgroup definitions, please see quality conformance inspection table. (2) subgroups apply to ? 55 c to +125 c column only. (3) fsr = full-scale range = 2 v ref . (4) f clk = 32.768-mhz max for high-speed mode and 27-mhz max for all other modes. when f clk > 27 mhz, operation is limited to frame- sync mode and v ref 2.6 v. (5) sps = samples per second. (6) best fit method. (7) worst-case channel crosstalk between one or more channels. (8) minimum snr is ensured by the limit of the dc noise specification. (9) thd includes the first nine harmonics of the input signal; low-speed mode includes the first five harmonics. 7.5 electrical characteristics all specifications at t a = ? 55 c to 125 c, avdd = 5 v, dvdd = 1.8 v, iovdd = 3.3 v, f clk = 27 mhz, vrefp = 2.5 v, vrefn = 0 v, and all channels active, unless otherwise noted. parameter test conditions subgroup (1) (2) ? 55 c to +125 c (ads1278mhfq-mls) ? 55 c to +115 c (ads1278whfq-mls) unit min typ max min typ max analog inputs full-scale input voltage (fsr (3) ) v in = (ainp ? ainn) v ref v ref v absolute input voltage ainp or ainn to agnd 1, 2, 3 agnd ? 0.1 avdd + 0.1 agnd ? 0.1 avdd + 0.1 v common-mode input voltage (v cm ) v cm = (ainp + ainn) / 2 2.5 2.5 v differential input impedance high-speed mode 14 14 k ? high-resolution mode 14 14 low-power mode 28 28 low-speed mode 140 140 dc performance resolution no missing codes 1, 2, 3 24 24 bits maximum data rate (f data ) high-speed mode f clk = 32.768 mhz (4) 128,000 128,000 sps (5) f clk = 27 mhz 105,469 105,469 high-resolution mode 52,734 52,734 low-power mode 52,734 52,734 low-speed mode 10,547 10,547 integral nonlinearity (inl) (6) differential input, v cm = 2.5 v 1, 2, 3 0.0003 0.001 2 0.0003 0.001 2 % fsr (3) offset error 1, 2, 3 0.25 2 0.25 2 mv offset drift 0.8 0.8 v/ c gain error 1, 2, 3 0.1 0.5 0.1 0.5 % fsr gain drift 1.3 1.3 ppm/ c noise high-speed mode shorted input 1, 2, 3 8.5 23 8.5 21 v, rms high-resolution mode shorted input 1, 2, 3 5.5 14 5.5 13 low-power mode shorted input 1, 2, 3 8.5 23 8.5 21 low-speed mode shorted input 1, 2, 3 8.0 23 8.0 21 common-mode rejection f cm = 60 hz 1, 2, 3 90 108 90 108 db power-supply rejection avdd f ps = 60 hz 80 80 db dvdd 85 85 iovdd 105 105 v com output voltage no load avdd / 2 avdd / 2 v ac performance crosstalk f = 1 khz, ? 0.5 dbfs (7) ? 107 ? 107 db signal-to-noise ratio (snr) (8) (unweighted) high-speed mode 4, 5, 6 98 106 98 106 db high-resolution mode v ref = 2.5 v 4, 5, 6 101 110 101 110 v ref = 3 v 111 111 low-power mode 4, 5, 6 98 106 98 106 low-speed mode 4, 5, 6 98 107 98 107 total harmonic distortion (thd) (9) v in = 1 khz, ? 0.5 dbfs 4, 5, 6 ? 108 -96 ? 108 -96 db spurious-free dynamic range 109 109 db advance information 8 ads1278-sp sbas937 ? september 2018 www.ti.com product folder links: ads1278-sp submit documentation feedback copyright ? 2018, texas instruments incorporated electrical characteristics (continued) all specifications at t a = ? 55 c to 125 c, avdd = 5 v, dvdd = 1.8 v, iovdd = 3.3 v, f clk = 27 mhz, vrefp = 2.5 v, vrefn = 0 v, and all channels active, unless otherwise noted. parameter test conditions subgroup (1) (2) ? 55 c to +125 c (ads1278mhfq-mls) ? 55 c to +115 c (ads1278whfq-mls) unit min typ max min typ max passband ripple 0.005 0.005 db passband 0.453 f data 0.453 f data hz ? 3-db bandwidth 0.49 f data 0.49 f data hz stop band attenuation high-resolution mode 4, 5, 6 95 95 db all other modes 4, 5, 6 100 100 db stop band high-resolution mode 4, 5, 6 0.547 f data 127.45 3 f data 0.547 f data 127.45 3 f data hz all other modes 4, 5, 6 0.547 f data 63.453 f data 0.547 f data 63.453 f data group delay high-resolution mode 39/f data 39/f data s all other modes 38/f data 38/f data settling time (latency) high-resolution mode complete settling 78/f data 78/f data s all other modes complete settling 76/f data 76/f data voltage reference inputs reference input voltage (v ref ) (v ref = vrefp ? vrefn) f clk = 27 mhz 1, 2, 3 0.5 2.5 3.1 0.5 2.5 3.1 v f clk = 32.768 mhz (4) 1, 2, 3 0.5 2.5 2.6 0.5 2.5 2.6 negative reference input (vrefn) 1, 2, 3 agnd ? 0.1 agnd + 0.1 agnd ? 0.1 agnd + 0.1 v positive reference input (vrefp) 1, 2, 3 vrefn + 0.5 avdd + 0.1 vrefn + 0.5 avdd + 0.1 v reference input impedance high-speed mode 0.65 0.65 k ? high-resolution mode 0.65 0.65 low-power mode 1.3 1.3 low-speed mode 6.5 6.5 digital input/output (iovdd = 1.8 v to 3.6 v) v ih 4, 5, 6 0.7 iovdd iovdd 0.7 iovdd iovdd v v il 4, 5, 6 dgnd 0.3 iovdd dgnd 0.3 iovdd v v oh i oh = 4 ma 4, 5, 6 0.8 iovdd iovdd 0.8 iovdd iovdd v v ol i ol = 4 ma 4, 5, 6 dgnd 0.2 iovdd dgnd 0.2 iovdd v input leakage 0 < v in digital < iovdd 4, 5, 6 11 10 a master clock rate (f clk ) high-speed mode (4) 4, 5, 6 0.1 32.768 0.1 32.768 mhz other modes 1, 2, 3 0.1 27 0.1 27 power supply avdd 1, 2, 3 4.75 5 5.25 4.75 5 5.25 v dvdd 1, 2, 3 1.65 1.8 1.95 1.65 1.8 1.95 v iovdd 1, 2, 3 1.65 3.6 1.65 3.6 v power-down current avdd 1, 2, 3 1 11 1 10 a dvdd 1, 2, 3 1 52 1 50 iovdd 1, 2, 3 1 12 1 11 avdd current high-speed mode 1, 2, 3 97 148 97 145 ma high-resolution mode 1, 2, 3 97 148 97 145 low-power mode 1, 2, 3 44 66 44 64 low-speed mode 1, 2, 3 9 15 9 14 advance information 9 ads1278-sp www.ti.com sbas937 ? september 2018 product folder links: ads1278-sp submit documentation feedback copyright ? 2018, texas instruments incorporated electrical characteristics (continued) all specifications at t a = ? 55 c to 125 c, avdd = 5 v, dvdd = 1.8 v, iovdd = 3.3 v, f clk = 27 mhz, vrefp = 2.5 v, vrefn = 0 v, and all channels active, unless otherwise noted. parameter test conditions subgroup (1) (2) ? 55 c to +125 c (ads1278mhfq-mls) ? 55 c to +115 c (ads1278whfq-mls) unit min typ max min typ max dvdd current high-speed mode 1, 2, 3 23 31 23 30 ma high-resolution mode 1, 2, 3 16 21 16 20 low-power mode 1, 2, 3 12 18 12 17 low-speed mode 1, 2, 3 2.5 5 2.5 4.5 iovdd current high-speed mode 1, 2, 3 0.25 1.5 0.25 1 ma high-resolution mode 1, 2, 3 0.125 0.8 0.125 0.6 low-power mode 1, 2, 3 0.125 0.8 0.125 0.6 low-speed mode 1, 2, 3 .035 0.5 0.035 0.3 power dissipation high-speed mode 1, 2, 3 530 805 530 785 mw high-resolution mode 1, 2, 3 515 785 515 765 low-power mode 1, 2, 3 245 370 245 355 low-speed mode 1, 2, 3 50 85 50 80 (1) timing parameters are characterized or assured by design for specified temperature but not production tested. (2) f clk = 27-mhz maximum. (3) depends on mode[1:0] and clkdiv selection. see table 5 (f clk / f data ). (4) load on drdy and dout = 20 pf. (5) for best performance, limit f sclk / f clk to ratios of 1, 1/2, 1/4, 1/8, etc.. (6) t dohd (dout hold time) and t dihd (din hold time) are specified under opposite worst-case conditions (digital supply voltage and ambient temperature). under equal conditions, with dout connected directly to din, the timing margin is > 4 ns. 7.6 timing requirements: spi format (1) for t a = ? 55 c to 125 c, iovdd = 1.65 v to 3.6 v, and dvdd = 1.65 v to 1.95 v. symbol parameter min typ max unit t clk clk period (1 / f clk ) (2) 37 10,000 ns t cpw clk positive or negative pulse width 15 ns t conv conversion period (1 / f data ) (3) 256 2560 t clk t cd (4) falling edge of clk to falling edge of drdy 22 ns t ds (4) falling edge of drdy to rising edge of first sclk to retrieve data 1 t clk t msbpd drdy falling edge to dout msb valid (propagation delay) 16 ns t sd (4) falling edge of sclk to rising edge of drdy 18 ns t sclk (5) sclk period 1 t clk t spw sclk positive or negative pulse width 0.4 t clk t dohd (4) (6) sclk falling edge to new dout invalid (hold time) 10 ns t dopd (4) sclk falling edge to new dout valid (propagation delay) 32 ns t dist new din valid to falling edge of sclk (setup time) 6 ns t dihd (6) old din valid to falling edge of sclk (hold time) 6 ns advance information 10 ads1278-sp sbas937 ? september 2018 www.ti.com product folder links: ads1278-sp submit documentation feedback copyright ? 2018, texas instruments incorporated figure 1. spi format timing characteristics advance information clk t cpw t clk t cpw t sd t sclk t dist t dohd t spw bit 23 (msb) bit 22 bit 21 t spw t dopd t cd t ds t msbpd t dihd t conv drdy sclk dout din 11 ads1278-sp www.ti.com sbas937 ? september 2018 product folder links: ads1278-sp submit documentation feedback copyright ? 2018, texas instruments incorporated (1) timing parameters are characterized or assured by design for specified temperature but not production tested. (2) depends on mode[1:0] and clkdiv selection. see table 5 (f clk / f data ). (3) sclk must be continuously running and limited to ratios of 1, 1/2, 1/4, and 1/8 of f clk . (4) t dohd (dout hold time) and t dihd (din hold time) are specified under opposite worst-case conditions (digital supply voltage and ambient temperature). under equal conditions, with dout connected directly to din, the timing margin is > 4 ns. (5) load on dout = 20 pf. 7.7 timing requirements: frame-sync format (1) over operating free-air temperature range (unless otherwise noted) symbol parameter min typ max unit t clk clk period (1 / f clk ) all modes 37 10,000 ns high-speed mode only 30.5 ns t cpw clk positive or negative pulse width 12 ns t cs falling edge of clk to falling edge of sclk ? 0.25 0.25 t clk t frame frame period (1 / f data ) (2) 256 2560 t clk t fpw fsync positive or negative pulse width 1 t sclk t fs rising edge of fsync to rising edge of sclk 5 ns t sf rising edge of sclk to rising edge of fsync 5 ns t sclk sclk period (3) 1 t clk t spw sclk positive or negative pulse width 0.4 t clk t dohd (4) (5) sclk falling edge to old dout invalid (hold time) 10 ns t dopd (5) sclk falling edge to new dout valid (propagation delay) 31 ns t msbpd fsync rising edge to dout msb valid (propagation delay) 31 ns t dist new din valid to falling edge of sclk (setup time) 6 ns t dihd (4) old din valid to falling edge of sclk (hold time) 6 ns figure 2. frame-sync format timing characteristics 7.8 quality conformance inspection mil-std-883, method 5005 - group a subgroup description temp ( c) 1 static tests at 25 2 static tests at 125 3 static tests at ? 55 4 dynamic tests at 25 5 dynamic tests at 125 6 dynamic tests at ? 55 7 functional tests at 25 advance information sclk fsync dout din t dohd t fpw t sclk t sf t spw t spw t frame t fpw t fs t dihd t msbpd t dist bit 23 (msb) bit 22 bit 21 t dopd clk t cpw t cpw t cs t clk 12 ads1278-sp sbas937 ? september 2018 www.ti.com product folder links: ads1278-sp submit documentation feedback copyright ? 2018, texas instruments incorporated quality conformance inspection (continued) subgroup description temp ( c) 8a functional tests at 125 8b functional tests at ? 55 9 switching tests at 25 10 switching tests at 125 11 switching tests at ? 55 12 setting time at 25 13 setting time at 125 14 setting time at ? 55 advance information 13 ads1278-sp www.ti.com sbas937 ? september 2018 product folder links: ads1278-sp submit documentation feedback copyright ? 2018, texas instruments incorporated 7.9 typical characteristics at t a = 25 c, high-speed mode, avdd = 5 v, dvdd = 1.8 v, iovdd = 3.3 v, f clk = 27 mhz, vrefp = 2.5 v, and vrefn = 0 v, unless otherwise noted. figure 3. output spectrum figure 4. output spectrum figure 5. output spectrum figure 6. noise histogram figure 7. output spectrum figure 8. output spectrum - 35 - 28 - 21 - 14 - 7 0 7 14 21 28 35 output ( v) m 25k20k 15k 10k 5k 0 number of occurrences high-speed modeshorted input 262,144 points 10 100 1k frequency (hz) 0 - 20 - 40 - 60 - 80 - 100 - 120 - 140 - 160 amplitude (db) 10k 100k high-speed mode f = 1khz, 0.5dbfs - in 32,768 points 10 100 1k frequency (hz) 0 - 20 - 40 - 60 - 80 - 100 - 120 - 140 - 160 amplitude (db) 10k 100k high-resolution mode f = 1khz, 20dbfs - in 32,768 points 1 10 100 1k frequency (hz) 0 - 20 - 40 - 60 - 80 - 100 - 120 - 140 - 160 - 180 amplitude (db) 10k 100k high-speed modeshorted input 262,144 points advance information 10 100 1k frequency (hz) 0 - 20 - 40 - 60 - 80 - 100 - 120 - 140 - 160 amplitude (db) 10k 100k high-resolution mode f = 1khz, 0.5dbfs - in 32,768 points 10 100 1k frequency (hz) 0 - 20 - 40 - 60 - 80 - 100 - 120 - 140 - 160 amplitude (db) 10k 100k high-speed mode f = 1khz, 20dbfs - in 32,768 points 14 ads1278-sp sbas937 ? september 2018 www.ti.com product folder links: ads1278-sp submit documentation feedback copyright ? 2018, texas instruments incorporated typical characteristics (continued) at t a = 25 c, high-speed mode, avdd = 5 v, dvdd = 1.8 v, iovdd = 3.3 v, f clk = 27 mhz, vrefp = 2.5 v, and vrefn = 0 v, unless otherwise noted. figure 9. output spectrum figure 10. noise histogram figure 11. output spectrum figure 12. output spectrum figure 13. output spectrum figure 14. noise histogram - 24.5 - 21.0 - 17.5 - 14.0 - 10.5 - 7.0 - 3.5 0 3.5 7.0 10.5 14.0 17.5 21.024.5 output ( v) m 25k20k 15k 10k 5k 0 number of occurrences high-resolution modeshorted input 262,144 points 10 100 1k frequency (hz) 0 - 20 - 40 - 60 - 80 - 100 - 120 - 140 - 160 amplitude (db) 10k 100k low-power mode f = 1khz, 20dbfs - in 32,768 points 1 10 100 1k frequency (hz) 0 - 20 - 40 - 60 - 80 - 100 - 120 - 140 - 160 - 180 amplitude (db) 10k 100k high-resolution modeshorted input 262,144 points 10 100 1k frequency (hz) 0 - 20 - 40 - 60 - 80 - 100 - 120 - 140 - 160 amplitude (db) 10k 100k low-power mode f = 1khz, 0.5dbfs - in 32,768 points advance information 1 10 100 1k frequency (hz) 0 - 20 - 40 - 60 - 80 - 100 - 120 - 140 - 160 - 180 amplitude (db) 10k 100k low-power mode shorted input 262,144 points - 37 - 32 - 26 - 21 - 16 - 11 - 5 0 5 11 16 21 26 32 37 output ( v) m 25k20k 15k 10k 5k 0 number of occurrences low-power mode shorted input 262,144 points 15 ads1278-sp www.ti.com sbas937 ? september 2018 product folder links: ads1278-sp submit documentation feedback copyright ? 2018, texas instruments incorporated typical characteristics (continued) at t a = 25 c, high-speed mode, avdd = 5 v, dvdd = 1.8 v, iovdd = 3.3 v, f clk = 27 mhz, vrefp = 2.5 v, and vrefn = 0 v, unless otherwise noted. figure 15. output spectrum figure 16. output spectrum figure 17. output spectrum figure 18. noise histogram figure 19. total harmonic distortion vs frequency figure 20. total harmonic distortion vs input amplitude - 35 - 28 - 21 - 14 - 7 0 7 14 21 28 35 output ( v) m 25k20k 15k 10k 5k 0 number of occurrences low-speed modeshorted input 262,144 points 1 10 100 frequency (hz) 0 - 20 - 40 - 60 - 80 - 100 - 120 - 140 - 160 amplitude (db) 1k 10k low-speed mode f = 100hz, 0.5dbfs - in 32,768 points 1 10 100 frequency (hz) 0 - 20 - 40 - 60 - 80 - 100 - 120 - 140 - 160 amplitude (db) 1k 10k low-speed mode f = 100hz, 20dbfs - in 32,768 points advance information - 120 - 100 - 80 - 60 - 40 input amplitude (dbfs) 0 - 20 - 40 - 60 - 80 - 100 - 120 - 140 thd, thd+n (db) - 20 0 high-speed mode f = 1khz in thd+n thd 10 100 1k frequency (hz) 0 - 20 - 40 - 60 - 80 - 100 - 120 - 140 thd, thd+n (db) 10k 100k high-speed mode v = 0.5dbfs - in thd+n thd 0.1 1 10 100 frequency (hz) 0 - 20 - 40 - 60 - 80 - 100 - 120 - 140 - 160 - 180 amplitude (db) 1k 10k low-speed modeshorted input 262,144 points 16 ads1278-sp sbas937 ? september 2018 www.ti.com product folder links: ads1278-sp submit documentation feedback copyright ? 2018, texas instruments incorporated typical characteristics (continued) at t a = 25 c, high-speed mode, avdd = 5 v, dvdd = 1.8 v, iovdd = 3.3 v, f clk = 27 mhz, vrefp = 2.5 v, and vrefn = 0 v, unless otherwise noted. figure 21. total harmonic distortion vs frequency figure 22. total harmonic distortion vs input amplitude figure 23. total harmonic distortion vs frequency figure 24. total harmonic distortion vs input amplitude figure 25. total harmonic distortion vs frequency figure 26. total harmonic distortion vs input amplitude 10 100 1k frequency (hz) 0 - 20 - 40 - 60 - 80 - 100 - 120 - 140 thd, thd+n (db) 10k low-speed mode v = 0.5dbfs - in thd+n thd - 120 - 100 - 80 - 60 - 40 input amplitude (dbfs) 0 - 20 - 40 - 60 - 80 - 100 - 120 - 140 thd, thd+n (db) - 20 0 low-speed mode thd+n thd 10 100 1k frequency (hz) 0 - 20 - 40 - 60 - 80 - 100 - 120 - 140 thd, thd+n (db) 10k 100k low-power mode v = 0.5dbfs - in thd+n thd - 120 - 100 - 80 - 60 - 40 input amplitude (dbfs) 0 - 20 - 40 - 60 - 80 - 100 - 120 - 140 thd, thd+n (db) - 20 0 high-resolution mode f = 1khz in thd+n thd advance information 10 100 1k frequency (hz) 0 - 20 - 40 - 60 - 80 - 100 - 120 - 140 thd, thd+n (db) 10k 100k high-resolution mode v = 0.5dbfs - in thd+n thd - 120 - 100 - 80 - 60 - 40 input amplitude (dbfs) 0 - 20 - 40 - 60 - 80 - 100 - 120 - 140 thd, thd+n (db) - 20 0 low-power mode f = 1khz in thd+n thd 17 ads1278-sp www.ti.com sbas937 ? september 2018 product folder links: ads1278-sp submit documentation feedback copyright ? 2018, texas instruments incorporated typical characteristics (continued) at t a = 25 c, high-speed mode, avdd = 5 v, dvdd = 1.8 v, iovdd = 3.3 v, f clk = 27 mhz, vrefp = 2.5 v, and vrefn = 0 v, unless otherwise noted. figure 27. offset drift histogram figure 28. gain drift histogram figure 29. offset warmup drift response band figure 30. gain warmup drift response band figure 31. offset error histogram figure 32. gain error histogram 0 50 100 150 200 250 300 350 time (s) 4030 20 10 0 - 10 - 20 - 30 - 40 normalized offset ( v) m 400 ads1278 low-speed mode ads1278 high-speed and high-resolution modes ads1278 low-power mode ads1274 high-speed and high-resolution modes 0 50 100 150 200 250 300 350 time (s) 4030 20 10 0 - 10 - 20 - 30 - 40 normalized gain error (ppm) 400 ads1274/78 high-speed and high-resolution modes ads1278 low-speed mode ads1278 low-power mode - 4000 - 3600 - 3200 - 2800 - 2400 - 2000 - 1600 - 1200 - 800 - 400 0 400800 12001600 2000 2400 2800 3200 3600 4000 gain error (ppm) 9080 70 60 50 40 30 20 10 0 number of occurrences high-speed mode25 units advance information - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 0 1 2 3 4 5 6 7 8 9 10 offset drift ( m v/ c) 400350 300 250 200 150 100 50 0 number of occurrences multi-lot data based on 20 c intervals over the range 40 c to +105 - c. - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 gain drift (ppm/ c) 900800 700 600 500 400 300 200 100 0 number of occurrences 25 units based on 20 c intervals over the range 40 c to +105 - c. outliers: t < 20 c - - 1000 - 900 - 800 - 700 - 600 - 500 - 400 - 300 - 200 - 100 0 100200 300 400 500 600 700 800 900 1000 offset ( v) m 4035 30 25 20 15 10 50 number of occurrences high-speed mode25 units 18 ads1278-sp sbas937 ? september 2018 www.ti.com product folder links: ads1278-sp submit documentation feedback copyright ? 2018, texas instruments incorporated typical characteristics (continued) at t a = 25 c, high-speed mode, avdd = 5 v, dvdd = 1.8 v, iovdd = 3.3 v, f clk = 27 mhz, vrefp = 2.5 v, and vrefn = 0 v, unless otherwise noted. figure 33. channel gain match histogram figure 34. channel offset match histogram figure 35. offset and gain vs temperature figure 36. vcom voltage output histogram figure 37. sampling match error histogram figure 38. reference input differential impedance vs temperature - 1500 - 1400 - 1300 - 1200 - 1100 - 1000 - 900 - 800 - 700 - 600 - 500 - 400 - 300 - 200 - 100 0 100200 300 400 500 600 700 800 900 10001100 1200 1300 1400 1500 channel offset match ( v) m 7060 50 40 30 20 10 0 number of occurrences high-speed mode10 units 0.62 0.63 0.64 0.65 0.66 0.67 0.68 -55 -40 -20 0 25 45 65 85 105 125 temperature (c) 6.2 6.3 6.4 6.5 6.6 6.7 6.8 reference input impedance (k ) w reference input impedance (k ) w high speed andhigh resolution low speed mode 50 100150 200 250 300 350 400 450 500 550 600 650 700 sampling match error (ps) 4035 30 25 20 15 10 50 number of occurrences 30 units over 3 production lots, inter-channel combinations. advance information -300 -200 -100 0 100 200 300 400 normalized offset ( v) m 600500 400 300 200 100 0 -100 -200 -300 normalized gain error (ppm) -55 -35 -15 5 25 45 65 85 105 125 temperature (c) offset gain 2.402.41 2.42 2.43 2.44 2.45 2.46 2.47 2.48 2.49 2.50 2.51 2.52 2.53 2.54 2.55 2.56 2.57 2.58 2.59 2.60 vcom voltage output (v) 2018 16 14 12 10 86 4 2 0 number of occurrences avdd = 5v 25 units, no load - 1500 - 1400 - 1300 - 1200 - 1100 - 1000 - 900 - 800 - 700 - 600 - 500 - 400 - 300 - 200 - 100 0 100200 300 400 500 600 700 800 900 10001100 1200 1300 1400 1500 channel gain match (ppm) 100 9080 70 60 50 40 30 20 10 0 number of occurrences high-speed mode10 units 19 ads1278-sp www.ti.com sbas937 ? september 2018 product folder links: ads1278-sp submit documentation feedback copyright ? 2018, texas instruments incorporated typical characteristics (continued) at t a = 25 c, high-speed mode, avdd = 5 v, dvdd = 1.8 v, iovdd = 3.3 v, f clk = 27 mhz, vrefp = 2.5 v, and vrefn = 0 v, unless otherwise noted. figure 39. analog input differential impedance vs temperature figure 40. analog input differential impedance vs temperature figure 41. integral nonlinearity vs temperature figure 42. linearity error vs input level figure 43. linearity and total harmonic distortion vs reference voltage figure 44. noise and linearity vs input common-mode voltage - 2.0 - 2.5 v (v) in 10 86 4 2 0 - 2 - 4 - 6 - 8 - 10 linearity error (ppm) 2.5 - 1.5 - 1.0 - 0.5 0 0.5 1.0 1.5 2.0 t = 40 c - t = +25 c t = +125 c t = +105 c 13.1 13.2 13.3 13.4 13.5 13.6 13.7 13.8 13.9 14 14.1 14.2 14.3 26.2 26.4 26.6 26.8 27 27.2 27.4 27.6 27.8 28 28.2 28.4 28.6 analog input impedance (k ) w analog input impedance (k ) w -55 -35 -15 5 25 45 65 85 105 125 temperature (c) high speed andhigh resolution low power mode low-speed mode -55 -35 -15 5 25 45 65 85 105 125 temperature (c) 110 120 130 140 150 160 170 analog input impedance (k ) w - 0.5 input common-mode voltage (v) 1412 10 86 4 2 0 rms noise ( v) m 1412 10 8 6 4 2 0 inl (ppm of fsr) 5.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 linearity noise advance information 0 v (v) ref 1412 10 86 4 2 0 linearity (ppm) - 100 - 104 - 108 - 112 - 116 - 120 - 124 - 128 thd (db) 3.5 thd 0.5 1.0 1.5 2.0 2.5 3.0 linearity thd: f = 1khz, v = 0.5dbfs in in - see for electrical characteristics v operating range. ref 0 2 4 6 8 10 inl (ppm of fsr) -55 -35 -15 5 25 45 65 85 105 125 temperature (c) 20 ads1278-sp sbas937 ? september 2018 www.ti.com product folder links: ads1278-sp submit documentation feedback copyright ? 2018, texas instruments incorporated typical characteristics (continued) at t a = 25 c, high-speed mode, avdd = 5 v, dvdd = 1.8 v, iovdd = 3.3 v, f clk = 27 mhz, vrefp = 2.5 v, and vrefn = 0 v, unless otherwise noted. figure 45. noise vs temperature figure 46. noise vs reference voltage figure 47. total harmonic distortion and noise vs clk figure 48. common-mode rejection vs input frequency figure 49. power-supply rejection vs power-supply frequency figure 50. avdd current vs temperature 0 20 40 60 80 100 120 140 160 avdd current (ma) -55 -35 -15 5 25 45 65 85 105 125 temperature (c) high speed and high resolution modes low power mode low speed mode 0 2 4 6 8 10 12 rms noise ( v) m -55 -35 -15 5 25 45 65 85 105 125 temperature (c) high resolution mode low power mode low speed mode high speed mode 0 0.5 v (v) ref 1210 86 4 2 0 noise ( v) m 3.5 1.0 1.5 2.0 2.5 3.0 see for electrical characteristics v operating range. ref low-power high-speed low-speed high-resolution 10k 100k clk (hz) 0 - 20 - 40 - 60 - 80 - 100 - 120 - 140 thd (db) 1412 10 8 6 4 2 0 noise rms ( v) m 100m 1m 10m high-speed mode f > 32.768mhz: v = 2.048v, dvdd = 2.1v thd: a = f /5120, 0.5dbfs clk ref in clk - noise: shorted input noise thd advance information 10 100 1k input frequency (hz) 0 - 20 - 40 - 60 - 80 - 100 - 120 common-mode rejection (db) 10k 100k 1m 10 100 1k power-supply modulation frequency (hz) 0 - 20 - 40 - 60 - 80 - 100 - 120 power-supply rejection (db) 10k 100k 1m avdd iovdd dvdd 21 ads1278-sp www.ti.com sbas937 ? september 2018 product folder links: ads1278-sp submit documentation feedback copyright ? 2018, texas instruments incorporated typical characteristics (continued) at t a = 25 c, high-speed mode, avdd = 5 v, dvdd = 1.8 v, iovdd = 3.3 v, f clk = 27 mhz, vrefp = 2.5 v, and vrefn = 0 v, unless otherwise noted. figure 51. dvdd current vs temperature figure 52. iovdd current vs temperature figure 53. power dissipation vs temperature 0 5 10 15 20 25 30 dvdd current (ma) high speed mode low power mode low speed mode high resolution mode -55 -35 -15 5 25 45 65 85 105 125 temperature (c) 0 100 200 300 400 500 600 700 800 power dissipation (mw) -55 -35 -15 5 25 45 65 85 105 125 temperature (c) high speed mode low power mode low speed mode high resolution mode 0 0.1 0.2 0.3 0.4 0.5 iovdd current (ma) -55 -35 -15 5 25 45 65 85 105 125 temperature (c) high speed mode high resolution and low power modes low speed mode advance information 22 ads1278-sp sbas937 ? september 2018 www.ti.com product folder links: ads1278-sp submit documentation feedback copyright ? 2018, texas instruments incorporated 8 detailed description 8.1 overview the ads1278-sp is a delta-sigma adc consisting of eight independent converters that digitize eight input signals in parallel. the converter is composed of two main functional blocks to perform the adc conversions: the modulator and the digital filter. the modulator samples the input signal together with sampling the reference voltage to produce a 1- s density output stream. the density of the output stream is proportional to the analog input level relative to the reference voltage. the pulse stream is filtered by the internal digital filter where the output conversion result is produced. in operation, the input signal is sampled by the modulator at a high rate (typically 64x higher than the final output data rate). the quantization noise of the modulator is moved to a higher frequency range where the internal digital filter removes it. oversampling results in very low levels of noise within the signal passband. since the input signal is sampled at a very high rate, input signal aliasing does not occur until the input signal frequency is at the modulator sampling rate. this architecture greatly relaxes the requirement of external antialiasing filters because of the high modulator sampling rate. the ads1278-sp is an octal 24-bit, delta-sigma adc. it offers the combination of outstanding dc accuracy and superior ac performance. functional block diagram section shows the block diagram. the converter is comprised of eight advanced, 6th-order, chopper-stabilized, delta-sigma modulators followed by low-ripple, linear phase fir filters. the modulators measure the differential input signal, v in = (ainp ? ainn), against the differential reference, v ref = (vrefp ? vrefn). the digital filters receive the modulator signal and provide a low-noise digital output. to allow tradeoffs among speed, resolution, and power, four operating modes are supported: high-speed, high-resolution, low-power, and low-speed. table 15 summarizes the performance of each mode. in high-speed mode, the maximum data rate is 128 ksps (when operating at 128 ksps, frame-sync format must be used). in high-resolution mode, the snr = 111 db (v ref = 3.0 v); in low-power mode, the power dissipation is 31 mw/channel; and in low-speed mode, the power dissipation is only 7 mw/channel at 10.5 ksps. the digital filters can be bypassed, enabling direct access to the modulator output. the ads1278-sp is configured by simply setting the appropriate i/o pins ? there are no registers to program. data are retrieved over a serial interface that supports both spi and frame-sync formats. the ads1278-sp has a daisy-chainable output and the ability to synchronize externally, so it can be used conveniently in systems requiring more than eight channels. advance information 23 ads1278-sp www.ti.com sbas937 ? september 2018 product folder links: ads1278-sp submit documentation feedback copyright ? 2018, texas instruments incorporated 8.2 functional block diagram 8.3 feature description 8.3.1 sampling aperture matching the ads1278-sp converter operates from the same clk input. the clk input controls the timing of the modulator sampling instant. the converter is designed such that the sampling skew, or modulator sampling aperture match between channels, is controlled. furthermore, the digital filters are synchronized to start the convolution phase at the same modulator clock cycle. this design results in excellent phase match among the ads1278-sp channels. figure 37 shows the inter-device channel sample matching for the ads1278-sp. 8.3.2 frequency response the digital filter sets the overall frequency response. the filter uses a multi-stage fir topology to provide linear phase with minimal passband ripple and high stop band attenuation. the filter coefficients are identical to the coefficients used in the ads1271 . the oversampling ratio of the digital filter (that is, the ratio of the modulator sampling to the output data rate, or f mod /f data ) is a function of the selected mode, as shown in table 1 . table 1. oversampling ratio vs mode mode selection oversampling ratio (f mod /f data ) high-speed 64 high-resolution 128 low-power 64 low-speed 64 ds modulator1 digitalfilter1 vrefp v in1 vrefnv ref s test[1:0] format[2:0] clk sync pwdn [8:1] clkdivmode[1:0] drdy /fsync sclk dout [8:1] din spi and frame-sync interface control logic ainp1 ainn1 vcom s ds modulator2 digitalfilter2 v in2 s ainp2 ainn2 ds modulator8 digital filter8 v in4/8 s ainp8 ainn8 dvdd avdd agnd dgnd iovdd r r modulator output mod 1mod 2 mod 8 advance information 24 ads1278-sp sbas937 ? september 2018 www.ti.com product folder links: ads1278-sp submit documentation feedback copyright ? 2018, texas instruments incorporated 8.3.2.1 high-speed, low-power, and low-speed modes the digital filter configuration is the same in high-speed, low-power, and low-speed modes with the oversampling ratio set to 64. figure 54 shows the frequency response in high-speed, low-power, and low- speed modes normalized to f data . figure 55 shows the passband ripple. the transition from passband to stop band is shown in figure 56 . the overall frequency response repeats at 64x multiples of the modulator frequency f mod , as shown in figure 57 . figure 54. frequency response for high-speed, low-power, and low-speed modes figure 55. passband response for high-speed, low-power, and low-speed modes 0.02 0 - 0.02 - 0.04 - 0.06 - 0.08 - 0.10 0.2 normalized input frequency (f /f in data ) amplitude (db) 0 0.1 0.3 0.4 0.5 0.6 0 - 20 - 40 - 60 - 80 - 100 - 120 - 140 0.4 normalized input frequency (f in /f data ) amplitude (db) 0 0.2 0.6 0.8 1.0 advance information 25 ads1278-sp www.ti.com sbas937 ? september 2018 product folder links: ads1278-sp submit documentation feedback copyright ? 2018, texas instruments incorporated figure 56. transition band response for high-speed, low-power, and low-speed modes figure 57. frequency response out to f mod for high-speed, low-power, and low-speed modes these image frequencies, if present in the signal and not externally filtered, will fold back (or alias) into the passband, causing errors. the stop band of the ads1278-sp provides 100-db attenuation of frequencies that begin just beyond the passband and continue out to f mod . placing an anti-aliasing, low-pass filter in front of the ads1278-sp inputs is recommended to limit possible high-amplitude, out-of-band signals and noise. often, a simple rc filter is sufficient. table 2 lists the image rejection versus external filter order. table 2. antialiasing filter order image rejection antialiasing filter order image rejection (db) (f ? 3db at f data ) hs, lp, ls hr 1 39 45 2 75 87 3 111 129 20 0 - 20 - 40 - 60 - 80 - 100 - 120 - 140 - 160 input frequency (f /f in data ) gain (db) 0 16 32 48 64 0 - 1 - 2 - 3 - 4 - 5 - 6 - 7 - 8 - 9 - 10 normalized input frequency (f /f in tda a ) amplitude (db) 0.45 0.47 0.49 0.51 0.53 0.55 advance information 26 ads1278-sp sbas937 ? september 2018 www.ti.com product folder links: ads1278-sp submit documentation feedback copyright ? 2018, texas instruments incorporated 8.3.2.2 high-resolution mode the oversampling ratio is 128 in high-resolution mode. figure 58 shows the frequency response in high- resolution mode normalized to f data . figure 59 shows the passband ripple, and the transition from passband to stop band is shown in figure 60 . the overall frequency response repeats at multiples of the modulator frequency f mod (128 f data ), as shown in figure 61 . the stop band of the ads1278-sp provides 100-db attenuation of frequencies that begin just beyond the passband and continue out to f mod . placing an antialiasing, low-pass filter in front of the ads1278-sp inputs is recommended to limit possible high-amplitude out-of-band signals and noise. often, a simple rc filter is sufficient. table 2 lists the image rejection versus external filter order. figure 58. frequency response for high-resolution mode figure 59. passband response for high-resolution mode 0.02 0 - 0.02 - 0.04 - 0.06 - 0.08 - 0.10 0.2 normalized input frequency (f /f in data ) amplitude (db) 0 0.1 0.3 0.4 0.5 0.6 advance information 0 - 20 - 40 - 60 - 80 - 100 - 120 - 140 0.50 normalized input frequency (f in /f data ) amplitude (db) 0 0.25 0.75 1 27 ads1278-sp www.ti.com sbas937 ? september 2018 product folder links: ads1278-sp submit documentation feedback copyright ? 2018, texas instruments incorporated figure 60. transition band response for high-resolution mode figure 61. frequency response out to f mod for high-resolution mode advance information 0 - 1 - 2 - 3 - 4 - 5 - 6 - 7 - 8 - 9 - 10 normalized input frequency (f /f in tda a ) amplitude (db) 0.45 0.47 0.49 0.51 0.53 0.55 20 0 - 20 - 40 - 60 - 80 - 100 - 120 - 140 - 160 gain (db) normalized input frequency (f /f in data ) 0 32 64 96 128 28 ads1278-sp sbas937 ? september 2018 www.ti.com product folder links: ads1278-sp submit documentation feedback copyright ? 2018, texas instruments incorporated 8.3.3 phase response the ads1278-sp incorporates a multiple stage, linear phase digital filter. linear phase filters exhibit constant delay time versus input frequency (constant group delay). this characteristic means the time delay from any instant of the input signal to the same instant of the output data is constant and is independent of input signal frequency. this behavior results in essentially zero phase errors when analyzing multi-tone signals. 8.3.4 settling time as with frequency and phase response, the digital filter also determines settling time. figure 62 shows the output settling behavior after a step change on the analog inputs normalized to conversion periods. the x-axis is given in units of conversion. note that after the step change on the input occurs, the output data change very little prior to 30 conversion periods. the output data are fully settled after 76 conversion periods for high-speed and low- power modes, and 78 conversion periods for high-resolution mode. figure 62. step response 8.3.5 data format the ads1278-sp outputs 24 bits of data in twos complement format. a positive full-scale input produces an ideal output code of 7fffffh, and the negative full-scale input produces an ideal output code of 800000h. the output clips at these codes for signals exceeding full-scale. table 3 summarizes the ideal output codes for different input signals. table 3. ideal output code versus input signal input signal v in (ainp ? ainn) ideal output code (1) +v ref 7fffffh 000001h 0 000000h ffffffh 800000h (1) excludes effects of noise, inl, offset, and gain errors. ?v ref 2 23 2 23 1 advance information 100 0 settling (%) conversions (1/f data ) 0 20 10 40 30 60 50 80 70 fully settled data at 76 conversions (78 conversions for high-resolution mode) initial value final value v ref 2 23 1 v ref 2 23 1 29 ads1278-sp www.ti.com sbas937 ? september 2018 product folder links: ads1278-sp submit documentation feedback copyright ? 2018, texas instruments incorporated 8.3.6 analog inputs (ainp, ainn) the ads1278-sp measures each differential input signal v in = (ainp ? ainn) against the common differential reference v ref = (vrefp ? vrefn). the most positive measurable differential input is +v ref , which produces the most positive digital output code of 7fffffh. likewise, the most negative measurable differential input is ? v ref , which produces the most negative digital output code of 800000h. for optimum performance, the inputs of the ads1278-sp are intended to be driven differentially. for single- ended applications, one of the inputs (ainp or ainn) can be driven while the other input is fixed (typically to agnd or 2.5 v). fixing the input to 2.5 v permits bipolar operation, thereby allowing full use of the entire converter range. while the ads1278-sp measures the differential input signal, the absolute input voltage is also important. this value is the voltage on either input (ainp or ainn) with respect to agnd. the range for this voltage is: ? 0.1 v < (ainn or ainp) < avdd + 0.1 v if either input is taken below ? 0.4 v or above (avdd + 0.4 v), esd protection diodes on the inputs may turn on. if these conditions are possible, external schottky clamp diodes or series resistors may be required to limit the input current to safe values (see the absolute maximum ratings table). the ads1278-sp is a very high-performance adc. for optimum performance, it is critical that the appropriate circuitry be used to drive the ads1278-sp inputs. see the application information section for several recommended circuits. advance information 30 ads1278-sp sbas937 ? september 2018 www.ti.com product folder links: ads1278-sp submit documentation feedback copyright ? 2018, texas instruments incorporated the ads1278-sp uses switched-capacitor circuitry to measure the input voltage. internal capacitors are charged by the inputs and then discharged. figure 63 shows a conceptual diagram of these circuits. switch s 2 represents the net effect of the modulator circuitry in discharging the sampling capacitor; the actual implementation is different. the timing for switches s 1 and s 2 is shown in figure 64 . the sampling time (t sample ) is the inverse of modulator sampling frequency (f mod ) and is a function of the mode, the clkdiv input, and clk frequency, as shown in table 4 . figure 63. equivalent analog input circuitry figure 64. s 1 and s 2 switch timing for figure 63 table 4. modulator frequency (f mod ) mode selection mode selection clkdiv f mod high-speed 1 f clk / 4 high-resolution 1 f clk / 4 low-power 1 f clk / 8 0 f clk / 4 low-speed 1 f clk / 40 0 f clk / 8 the average load presented by the switched capacitor input can be modeled with an effective differential impedance, as shown in figure 65 . note that the effective impedance is a function of f mod . figure 65. effective input impedances on off s 1 on off s 2 t sample mod = 1/f esd protection avdd agnd avdd ainp 9pf ainn agnd s 1 s 1 s 2 advance information ainp ainn z = 14k eff mo w (6.75mhz/f d ) 31 ads1278-sp www.ti.com sbas937 ? september 2018 product folder links: ads1278-sp submit documentation feedback copyright ? 2018, texas instruments incorporated 8.3.7 voltage reference inputs (vrefp, vrefn) the voltage reference for the ads1278-sp adc is the differential voltage between vrefp and vrefn: v ref = (vrefp ? vrefn). the voltage reference is common to all channels. the reference inputs use a structure similar to that of the analog inputs with the equivalent circuitry on the reference inputs shown in figure 66 . as with the analog inputs, the load presented by the switched capacitor can be modeled with an effective impedance, as shown in figure 67 . however, the reference input impedance depends on the number of active (enabled) channels in addition to f mod . as a result of the change of reference input impedance caused by enabling and disabling channels, the regulation and setting time of the external reference should be noted, so as not to affect the readings. figure 66. equivalent reference input circuitry figure 67. effective reference impedance esd diodes protect the reference inputs. to keep these diodes from turning on, make sure the voltages on the reference pins do not go below agnd by more than 0.4 v, and likewise do not exceed avdd by 0.4 v. if these conditions are possible, external schottky clamp diodes or series resistors may be required to limit the input current to safe values (see the absolute maximum ratings table). note that the valid operating range of the reference inputs is limited to the following parameters: ? 0.1 v vrefn +0.1 v vrefn + 0.5 v vrefp avdd + 0.1 v 8.3.8 clock input (clk) the ads1278-sp requires a clock input for operation. the individual converters of the ads1278-sp operate from the same clock input. at the maximum data rate, the clock input can be either 27 mhz or 13.5 mhz for low- power mode, or 27mhz or 5.4 mhz for low-speed mode, determined by the setting of the clkdiv input. for high-speed mode, the maximum clk input frequency is 32.768 mhz. for high-resolution mode, the maximum clk input frequency is 27 mhz. the selection of the external clock frequency (f clk ) does not affect the resolution of the ads1278-sp. use of a slower f clk can reduce the power consumption of an external clock buffer. the output data rate scales with clock frequency, down to a minimum clock frequency of f clk = 100 khz. table 5 summarizes the ratio of the clock input frequency (f clk ) to data rate (f data ), maximum data rate and corresponding maximum clock input for the four operating modes. advance information vrefp vrefn z = eff (6.75mhz/f ) mod 5.2k w n n = number of active channels. esd protection avdd avdd vrefn vrefp agnd agnd 32 ads1278-sp sbas937 ? september 2018 www.ti.com product folder links: ads1278-sp submit documentation feedback copyright ? 2018, texas instruments incorporated as with any high-speed data converter, a high-quality, low-jitter clock is essential for optimum performance. crystal clock oscillators are the recommended clock source. make sure to avoid excess ringing on the clock input; keeping the clock trace as short as possible, and using a 50- ? series resistor placed close to the source end, often helps. table 5. clock input options mode selection max f clk (mhz) clkdiv f clk /f data data rate (sps) high-speed 32.768 1 256 128,000 high-resolution 27 1 512 52,734 low-power 27 1 512 52,734 13.5 0 256 low-speed 27 1 2,560 10,547 5.4 0 512 8.3.9 mode selection (mode) the ads1278-sp supports four modes of operation: high-speed, high-resolution, low-power, and low-speed. the modes offer optimization of speed, resolution, and power. mode selection is determined by the status of the digital input mode[1:0] pins, as shown in table 6 . the ads1278-sp continually monitors the status of the mode pin during operation. table 6. mode selection mode[1:0] mode selection max f data (1) 00 high-speed 128,000 01 high-resolution 52,734 10 low-power 52,734 11 low-speed 10,547 (1) f clk = 27-mhz max (32.768-mhz max in high-speed mode). when using the spi protocol, drdy is held high after a mode change occurs until settled (or valid) data are ready; see figure 68 and table 7 . in frame-sync protocol, the dout pins are held low after a mode change occurs until settled data are ready; see figure 68 and table 7 . data can be read from the device to detect when dout changes to logic 1, indicating that the data are valid. advance information 33 ads1278-sp www.ti.com sbas937 ? september 2018 product folder links: ads1278-sp submit documentation feedback copyright ? 2018, texas instruments incorporated figure 68. mode change timing table 7. new data after mode change symbol description min typ max units t ndr-spi time for new data to be ready (spi) 129 conversions (1/f data ) t ndr-fs time for new data to be ready (frame-sync) 127 128 conversions (1/f data ) 8.3.10 synchronization ( sync) the ads1278-sp can be synchronized by pulsing the sync pin low and then returning the pin high. when the pin goes low, the conversion process stops, and the internal counters used by the digital filter are reset. when the sync pin returns high, the conversion process restarts. synchronization allows the conversion to be aligned with an external event, such as the changing of an external multiplexer on the analog inputs, or by a reference timing pulse. because the ads1278-sp converters operate in parallel from the same master clock and use the same sync input control, they are always in synchronization with each other. the aperture match among internal channels is typically less than 500 ps. however, the synchronization of multiple devices is somewhat different. at device power-on, variations in internal reset thresholds from device to device may result in uncertainty in conversion timing. the sync pin can be used to synchronize multiple devices to within the same clk cycle. figure 69 illustrates the timing requirement of sync and clk in spi format. see figure 70 for the frame-sync format timing requirement. after synchronization, indication of valid data depends on whether spi or frame-sync format was used. in the spi format, drdy goes high as soon as sync is taken low; see figure 69 . after sync is returned high, drdy stays high while the digital filter is settling. once valid data are ready for retrieval, drdy goes low. in the frame-sync format, dout goes low as soon as sync is taken low; see figure 70 . after sync is returned high, dout stays low while the digital filter is settling. once valid data are ready for retrieval, dout begins to output valid data. for proper synchronization, fsync, sclk, and clk must be established before taking sync high, and must then remain running. if the clock inputs (clk, fsync or sclk) are subsequently interrupted or reset, re-assert the sync pin. for consistent performance, re-assert sync after device power-on when data first appear. advance information mode[1:0] pins ads1278 mode new mode new mode valid data ready drdy spi protocol frame-sync protocol t ndr-spi dout new mode valid data on dout t ndr-fs previous mode 34 ads1278-sp sbas937 ? september 2018 www.ti.com product folder links: ads1278-sp submit documentation feedback copyright ? 2018, texas instruments incorporated figure 69. synchronization timing (spi protocol) table 8. spi protocol symbol description min typ max units t cshd clk to sync hold time 10 ns t scsu sync to clk setup time 5 ns t syn synchronize pulse width 1 clk periods t ndr time for new data to be ready 129 conversions (1/f data ) figure 70. synchronization timing (frame-sync protocol) table 9. frame-sync protocol symbol description min typ max units t cshd clk to sync hold time 10 ns t scsu sync to clk setup time 5 ns t syn synchronize pulse width 1 clk periods t ndr time for new data to be ready 127 128 conversions (1/f data ) advance information clk drdy sync t ndr t syn t scsu t cshd fsync valid data dout sync t ndr t syn clk t cshd t scsu 35 ads1278-sp www.ti.com sbas937 ? september 2018 product folder links: ads1278-sp submit documentation feedback copyright ? 2018, texas instruments incorporated 8.3.11 power-down ( pwdn) the channels of the ads1278-sp can be independently powered down by use of the pwdn inputs. to enter the power-down mode, hold the respective pwdn pin low for at least two clk cycles. to exit power-down, return the corresponding pwdn pin high. note that when all channels are powered down, the ads1278-sp enters a microwatt ( w) power state where all internal biasing is disabled. in this state, the test[1:0] input pins must be driven; all other input pins can float. the ads1278-sp outputs remain driven. as shown in figure 71 and table 10 , a maximum of 130 conversion cycles must elapse for spi interface, and 129 conversion cycles must elapse for frame-sync, before reading data after exiting power-down. data from channels already running are not affected. the user software can perform the required delay time in any of the following ways: 1. count the number of data conversions after taking the pwdn pin high. 2. delay 129/f data or 130/f data after taking the pwdn pins high, then read data. advance information 36 ads1278-sp sbas937 ? september 2018 www.ti.com product folder links: ads1278-sp submit documentation feedback copyright ? 2018, texas instruments incorporated 3. detect for non-zero data in the powered-up channel. after powering up one or more channels, the channels are synchronized to each other. it is not necessary to use the sync pin to synchronize them. when a channel is powered down in tdm data format, the data for that channel are either forced to zero (fixed- position tdm data mode) or replaced by shifting the data from the next channel into the vacated data position (dynamic-position tdm data mode). in discrete data format, the data are always forced to zero. when powering-up a channel in dynamic-position tdm data format mode, the channel data remain packed until the data are ready, at which time the data frame is expanded to include the just-powered channel data. see the data format section for details. figure 71. power-down timing table 10. power-down timing symbol description min typ max units t pwdn pwdn pulse width to enter power-down mode 2 clk periods t ndr time for new data ready (spi) 129 130 conversions (1/f data ) t ndr time for new data ready (frame-sync) 128 129 conversions (1/f data ) advance information clk drdy/fsync (1) dout (discrete data output mode) pwdn t ndr t pwdn p -up data ost power dout1 (tdm mode, dynamic position) normal position normal position data shifts position normal position normal position data remains in position dout1 (tdm mode, fixed position) 37 ads1278-sp www.ti.com sbas937 ? september 2018 product folder links: ads1278-sp submit documentation feedback copyright ? 2018, texas instruments incorporated 8.3.12 format[2:0] data can be read from the ads1278-sp with two interface protocols (spi or frame-sync) and several options of data formats (tdm/discrete and fixed/dynamic data positions). the format[2:0] inputs are used to select among the options. table 11 lists the available options. see the dout modes section for details of the dout mode and data position. table 11. data output format format[2:0] interface protocol dout mode data position 000 spi tdm dynamic 001 spi tdm fixed 010 spi discrete ? 011 frame-sync tdm dynamic 100 frame-sync tdm fixed 101 frame-sync discrete ? 110 modulator mode ? ? 8.3.13 serial interface protocols data are retrieved from the ads1278-sp using the serial interface. two protocols are available: spi and frame- sync. the same pins are used for both interfaces: sclk, drdy/fsync, dout[8:1], and din. the format[2:0] pins select the desired interface protocol. 8.3.14 spi serial interface the spi-compatible format is a read-only interface. data ready for retrieval are indicated by the falling drdy output and are shifted out on the falling edge of sclk, msb first. the interface can be daisy-chained using the din input when using multiple devices. see the daisy-chaining section for more information. note: the spi format is limited to a clk input frequency of 27 mhz, maximum. for clk input operation above 27 mhz (high-speed mode only), use frame-sync format. 8.3.14.1 sclk the serial clock (sclk) features a schmitt-triggered input and shifts out data on dout on the falling edge. it also shifts in data on the falling edge on din when this pin is being used for daisy-chaining. the device shifts data out on the falling edge and the user normally shifts this data in on the rising edge. even though the sclk input has hysteresis, it is recommended to keep sclk as clean as possible to prevent glitches from accidentally shifting the data. sclk may be run as fast as the clk frequency. sclk may be either in free-running or stop-clock operation between conversions. note that one f clk is required after the falling edge of drdy until the first rising edge of sclk. for best performance, limit f sclk / f clk to ratios of 1, 1/2, 1/4, 1/8, etc. when the device is configured for modulator output, sclk becomes the modulator clock output (see the modulator output section). 8.3.14.2 drdy/fsync (spi format) in the spi format, this pin functions as the drdy output. it goes low when data are ready for retrieval and then returns high on the falling edge of the first subsequent sclk. if data are not retrieved (that is, sclk is held low), drdy pulses high just before the next conversion data are ready, as shown in figure 72 . the new data are loaded within one clk cycle before drdy goes low. all data must be shifted out before this time to avoid being overwritten. figure 72. drdy timing with no readback advance information drdy sclk 1/f data 1/f clk 38 ads1278-sp sbas937 ? september 2018 www.ti.com product folder links: ads1278-sp submit documentation feedback copyright ? 2018, texas instruments incorporated 8.3.14.3 dout the conversion data are output on dout[8:1]. the msb data are valid on dout[8:1] after drdy goes low. subsequent bits are shifted out with each falling edge of sclk. if daisy-chaining, the data shifted in using din appear on dout after all channel data have been shifted out. when the device is configured for modulator output, dout[8:1] becomes the modulator data output for each channel (see the modulator output section). 8.3.14.4 din this input is used when multiple ads1278-sps are to be daisy-chained together. the dout1 pin of the first device connects to the din pin of the next, etc. it can be used with either the spi or frame-sync formats. data are shifted in on the falling edge of sclk. when using only one ads1278-sp, tie din low. see the daisy- chaining section for more information. advance information 39 ads1278-sp www.ti.com sbas937 ? september 2018 product folder links: ads1278-sp submit documentation feedback copyright ? 2018, texas instruments incorporated 8.3.15 frame-sync serial interface frame-sync format is similar to the interface often used on audio adcs. it operates in slave fashion ? the user must supply framing signal fsync (similar to the left/right clock on stereo audio adcs) and the serial clock sclk (similar to the bit clock on audio adcs). the data are output msb first or left-justified on the rising edge of fsync. when using frame-sync format, the fsync and sclk inputs must be continuously running with the relationships shown in the timing requirements: frame-sync format table. 8.3.15.1 sclk the serial clock (sclk) features a schmitt-triggered input and shifts out data on dout on the falling edge. it also shifts in data on the falling edge on din when this pin is being used for daisy-chaining. even though sclk has hysteresis, it is recommended to keep sclk as clean as possible to prevent glitches from accidentally shifting the data. when using frame-sync format, sclk must run continuously. if it is shut down, the data readback will be corrupted. the number of sclks within a frame period (fsync clock) can be any power-of-2 ratio of clk cycles (1, 1/2, 1/4, etc), as long as the number of cycles is sufficient to shift the data output from all channels within one frame. when the device is configured for modulator output, sclk becomes the modulator clock output (see the modulator output section). 8.3.15.2 drdy/fsync (frame-sync format) in frame-sync format, this pin is used as the fsync input. the frame-sync input (fsync) sets the frame period, which must be the same as the data rate. the required number of f clk cycles to each fsync period depends on the mode selection and the clkdiv input. table 5 indicates the number of clk cycles to each frame (f clk /f data ). if the fsync period is not the proper value, data readback will be corrupted. 8.3.15.3 dout the conversion data are shifted out on dout[8:1]. the msb data become valid on dout[8:1] after fsync goes high. the subsequent bits are shifted out with each falling edge of sclk. if daisy-chaining, the data shifted in using din appear on dout[8:1] after all channel data have been shifted out. when the device is configured for modulator output, dout becomes the modulator data output (see the modulator output section). 8.3.15.4 din this input is used when multiple ads1278-sps are to be daisy-chained together. it can be used with either spi or frame-sync formats. data are shifted in on the falling edge of sclk. when using only one ads1278-sp, tie din low. see the daisy-chaining section for more information. 8.3.16 dout modes for both spi and frame-sync interface protocols, the data are shifted out either through individual channel dout pins, in a parallel data format (discrete mode), or the data for all channels are shifted out, in a serial format, through a common pin, dout1 (tdm mode). 8.3.16.1 tdm mode in tdm (time-division multiplexed) data output mode, the data for all channels are shifted out, in sequence, on a single pin (dout1). as shown in figure 73 , the data from channel 1 are shifted out first, followed by channel 2 data, etc. after the data from the last channel are shifted out, the data from the din input follow. the din is used to daisy-chain the data output from an additional ads1278-sp or other compatible device. note that when all channels of the ads1278-sp are disabled, the interface is disabled, rendering the din input disabled as well. when one or more channels of the device are powered down, the data format of the tdm mode can be fixed or dynamic. advance information 40 ads1278-sp sbas937 ? september 2018 www.ti.com product folder links: ads1278-sp submit documentation feedback copyright ? 2018, texas instruments incorporated figure 73. tdm mode (all channels enabled) 8.3.16.2 tdm mode, fixed-position data in this tdm data output mode, the data position of the channels remain fixed, regardless of whether the channels are powered down. if a channel is powered down, the data are forced to zero but occupy the same position within the data stream. figure 74 shows the data stream with channel 1 and channel 3 powered down. 8.3.16.3 tdm mode, dynamic position data in this tdm data output mode, when a channel is powered down, the data from higher channels shift one position in the data stream to fill the vacated data slot. figure 75 shows the data stream with channel 1 and channel 3 powered down. 8.3.16.4 discrete data output mode in discrete data output mode, the channel data are shifted out in parallel using individual channel data output pins dout[8:1]. after the 24th sclk, the channel data are forced to zero. the data are also forced to zero for powered down channels. figure 76 shows the discrete data output format. figure 74. tdm mode, fixed-position data (channels 1 and 3 shown powered down) figure 75. tdm mode, dynamic position data (channels 1 and 3 shown powered down) sclk drdy (spi) fsync (frame-sync) 1 2 24 25 23 48 49 47 72 73 71 96 97 95 ch1 dout1 169 ch2 ch3 ch4 ch5 191 ch8 din 192 193 194 195 ch7 168 167 sclk drdy (spi) fsync (frame-sync) 1 2 24 25 23 48 49 47 72 73 71 96 97 95 ch1 dout1 ch2 ch3 ch5 ch4 ch8 din ch7 169 191 192 193 194 195 168 167 advance information sclk drdy (spi) fsync (frame- sync) 1 2 24 25 23 48 49 47 50 ch2 dout1 ch4 ch5 ch8 din 143 144 145 145 146 121 120 ch7 119 41 ads1278-sp www.ti.com sbas937 ? september 2018 product folder links: ads1278-sp submit documentation feedback copyright ? 2018, texas instruments incorporated figure 76. discrete data output mode 8.3.17 daisy-chaining multiple ads1278-sps can be daisy-chained together to output data on a single pin. the dout1 data output pin of one device is connected to the din of the next device. as shown in figure 77 , the dout1 pin of device 1 provides the output data to a controller, and the din of device 2 is grounded. figure 78 shows the data format when reading back data. the maximum number of channels that may be daisy-chained in this way is limited by the frequency of f sclk , the mode selection, and the clkdiv input. the frequency of f sclk must be high enough to completely shift the data out from all channels within one f data period. table 12 lists the maximum number of daisy-chained channels when f sclk = f clk . to increase the number of data channels possible in a chain, a segmented dout scheme may be used, producing two data streams. figure 79 illustrates four ads1278-sps, with pairs of ads1278-sps daisy-chained together. the channel data of each daisy-chained pair are shifted out in parallel and received by the processor through independent data channels. table 12. maximum channels in a daisy-chain (f sclk = f clk ) mode selection clkdiv maximum number of channels high-speed 1 10 high-resolution 1 21 low-power 1 21 0 10 low-speed 1 106 0 21 whether the interface protocol is spi or frame-sync, it is recommended to synchronize all devices by tying the sync inputs together. when synchronized in spi protocol, it is only necessary to monitor the drdy output of one ads1278-sp. in frame-sync interface protocol, the data from all devices are ready after the rising edge of fsync. since dout1 and din are both shifted on the falling edge of sclk, the propagation delay on dout1 creates a setup time on din. minimize the skew in sclk to avoid timing violations. ch1 dout1 ch2 dout2 ch3 dout3 ch4 dout4 sclk drdy (spi) fsync (frame-sync) 1 2 22 23 24 ch5 dout5 ch6 dout6 ch7 dout7 ch8 dout8 25 26 advance information 42 ads1278-sp sbas937 ? september 2018 www.ti.com product folder links: ads1278-sp submit documentation feedback copyright ? 2018, texas instruments incorporated note: the number of chained devices is limited by the sclk rate and device mode. figure 77. daisy-chaining of two devices, spi protocol (format[2:0] = 000 or 001) figure 78. daisy-chain data format of figure 77 note: the number of chained devices is limited by the sclk rate and device mode. figure 79. segmented dout daisy-chain, frame-sync protocol (format[2:0] = 011 or 100) 8.3.18 modulator output the ads1278-sp incorporates a 6th-order, single-bit, chopper-stabilized modulator followed by a multi-stage digital filter that yields the conversion results. the data stream output of the modulator is available directly, bypassing the internal digital filter. the digital filter is disabled, reducing the dvdd current, as shown in table 13 . in this mode, an external digital filter implemented in an asic, fpga, or similar device is required. to invoke the modulator output, tie format[2:0], as shown in figure 80 . dout[8:1] then becomes the modulator data stream outputs for each channel and sclk becomes the modulator clock output. the drdy/fsync pin becomes an unused output and can be ignored. the normal operation of the frame-sync and spi interfaces is disabled, and the functionality of sclk changes from an input to an output, as shown in figure 80 . sync fsync dout1 sync sclk fsync sclk sync din clk clk fsync dout1 sclk sync fsync dout1 sclk sync din fsync dout1 serial data devices 1 and 2 serial data devices 3 and 4 sclk clk clk clk din din u4 u3 u2 u1 advance information sync clk sync din dout1 sclk sclk sync din clk clk dout1 drdy dout from devices 1 and 2 drdy output from device 1 sclk u2 u1 ch1, u1 dout1 ch2, u1 ch3, u1 ch4, u1 ch5, u1 ch1, u2 ch2, u2 din2 sclk drdy (spi) fsync (frame-sync) 1 2 25 49 26 50 73 74 97 98 193 194 217 218 385 386 43 ads1278-sp www.ti.com sbas937 ? september 2018 product folder links: ads1278-sp submit documentation feedback copyright ? 2018, texas instruments incorporated table 13. modulator output clock frequencies mode [1:0] clkdiv modulator clock output (sclk) dvdd (ma) 00 1 f clk / 4 8 01 1 f clk / 4 7 10 1 f clk / 8 4 0 f clk / 4 4 11 1 f clk / 40 1 0 f clk / 8 1 figure 80. modulator output advance information format0 din modulator clock output iovdd sclk format1 format2 modulator data channel 2 dout2 modulator data channel 1 dout1 modulator data channel 8 dout8 44 ads1278-sp sbas937 ? september 2018 www.ti.com product folder links: ads1278-sp submit documentation feedback copyright ? 2018, texas instruments incorporated in modulator output mode, the frequency of the modulator clock output (sclk) depends on the mode selection of the ads1278-sp. table 13 lists the modulator clock output frequency and dvdd current versus device mode. figure 81 shows the timing relationship of the modulator clock and data outputs. the data output is a modulated 1s density data stream. when v in = +v ref , the 1s density is approximately 80% and when v in = ? v ref , the 1s density is approximately 20%. figure 81. modulator output timing 8.3.19 pin test using test[1:0] inputs the test mode feature of the ads1278-sp allows continuity testing of the digital i/o pins. in this mode, the normal functions of the digital pins are disabled and routed to each other as pairs through internal logic, as shown in table 14 . the pins in the left column drive the output pins in the right column. note: some of the digital input pins become outputs; these outputs must be accommodated in the design. the analog input, power supply, and ground pins all remain connected as normal. the test mode is engaged by setting the pins test [1:0] = 11. for normal converter operation, set test[1:0] = 00. do not use '01' or '10'. table 14. test mode pin map (test[1:0] = 11) test mode pin map input pins output pins pwdn1 dout1 pwdn2 dout2 pwdn3 dout3 pwdn4 dout4 pwdn5 dout5 pwdn6 dout6 pwdn7 dout7 pwdn8 dout8 mode0 din mode1 sync format0 clkdiv format1 fsync/ drdy format2 sclk 8.3.20 vcom output the vcom pin provides a voltage output equal to avdd / 2. the intended use of this output is to set the output common-mode level of the analog input drivers. the drive capability of the output is limited; therefore, the output should only be used to drive high-impedance nodes ( > 1 m ? ). in some cases, an external buffer may be necessary. a 0.1- f bypass capacitor is recommended to reduce noise pickup. figure 82. vcom output advance information sclk dout modulator clock output modulator data output (13ns max) 0.1 f vcom vdd/2) (a? lm124aqml-sp 45 ads1278-sp www.ti.com sbas937 ? september 2018 product folder links: ads1278-sp submit documentation feedback copyright ? 2018, texas instruments incorporated 8.4 device functional modes table 15. operating mode performance summary mode max data rate (sps) passband (khz) snr (db) noise ( v rms ) power/channel (mw) high-speed 128,000 57,984 106 8.5 70 high-resolution 52,734 23,889 110 5.5 64 low-power 52,734 23,889 106 8.5 31 low-speed 10,547 4,798 107 8.0 7 advance information 46 ads1278-sp sbas937 ? september 2018 www.ti.com product folder links: ads1278-sp submit documentation feedback copyright ? 2018, texas instruments incorporated 9 application and implementation note information in the following applications sections is not part of the ti component specification, and ti does not warrant its accuracy or completeness. ti ? s customers are responsible for determining suitability of components for their purposes. customers should validate and test their design implementation to confirm system functionality. 9.1 application information the ads1278-sp is a radiation-hardened high resolution delta-sigma adc that is ideal for precision sensing and high accuracy instrumentation applications. with eight simultaneous sampling 24-bit adcs integrated, the device reduces the board area needed to digitize eight analog signals. 9.2 typical application figure 83. typical application schematic 9.2.1 design requirements depending on the accuracy and speed requirements of the sensing application to be digitized by the adc1278- sp, users must first determine the optimal device configuration. table 16 shows the possible configurations for device for the maximum fclkin for each configuration. the yellow highlighted columns indicate user defined inputs (through i/o pins) to the device, while the italic row indicates the default configuration of the ads1278evm-cval evm that is available as a reference design. as shown, a maximum data rate of 52734 sps is possible while using the high resolution mode, which yields a typical snr of 111 db or an enob of 18 bits. advance information in1(+) ainp1ainn1 in4/8(+) +3.3 v +1.8 v (6) ainp4/8ainn4/8 avdd dvdd vrefp vrefn vcom test0 test1 din agnd dgnd iovdd clk drdy/fsync dvdd (i/o)dr fsr dout1 sclk cvdd (core) dout2dout3 dout4 sync pwdn1 i/o pwdn2 pwdn3 pwdn4 clkdiv format2 mode1 format1 format0 10 f (2) + 10 f (2) 10 f + 0.1 f (2) 0.1 f (2) lm4050qml-sp +5 v 10 f (2) 50 +3.3 v (high-speed, frame-sync, tdm, and fixed-position data selected.) ads1278-sp microcontroller / dsp 200 mhz +1.6 v ths4521 (1) 2.2 nf (3) 2.2 nf (3) (4) buffered vcom output 100 see note (5) 50 u1 u2 clkr qq 0> +3.3 v mode0 in1(-) ... ... in4/8(-) 1 f +5 v seenote (6) lm124aqml-sp 47 ads1278-sp www.ti.com sbas937 ? september 2018 product folder links: ads1278-sp submit documentation feedback copyright ? 2018, texas instruments incorporated typical application (continued) table 16. ads1278-sp configuration modes mode clkdiv fclk/fmod fclkin_max (mhz) oversampling (fmod/fdata) fmod (mhz) fdata_max (sps) fclkin/fmod high-speed 1 4 32.768 64 8.192 128000 4 high-speed 1 4 32.768 64 8.192 128000 4 high-speed 1 4 27 64 6.75 105469 4 high resolution 1 4 27 128 6.75 52734 4 low-power 1 8 27 64 3.375 52734 8 low-power 0 4 13.5 64 3.375 52734 4 low-speed 1 40 27 64 0.675 10547 40 low-speed 0 8 5.4 64 0.675 10547 8 9.2.2 detailed design procedure to obtain the specified performance from the ads1278-sp, the following layout and component guidelines should be considered. 1. power supplies: the device requires three power supplies for operation: dvdd, iovdd, and avdd. the allowed range for dvdd is 1.65 v to 1.95 v; the range of iovdd is 1.65 v to 3.6 v; avdd is restricted to 4.75 v to 5.25 v. for all supplies, use a 10- f tantalum capacitor, bypassed with a 0.1- f ceramic capacitor, placed close to the device pins. alternatively, a single 10- f ceramic capacitor can be used. the supplies should be relatively free of noise and should not be shared with devices that produce voltage spikes (such as relays, led display drivers, etc.). if a switching power-supply source is used, the voltage ripple should be low (less than 2 mv) and the switching frequency outside the passband of the converter. 2. ground plane: a single ground plane connecting both agnd and dgnd pins can be used. if separate digital and analog grounds are used, connect the grounds together at the converter. 3. digital inputs: it is recommended to source-terminate the digital inputs to the device with 50- ? series resistors. the resistors should be placed close to the driving end of digital source (oscillator, logic gates, dsp, etc.) this placement helps to reduce ringing on the digital lines (ringing may lead to degraded adc performance). 4. analog/digital circuits: place analog circuitry (input buffer, reference) and associated tracks together, keeping them away from digital circuitry (dsp, microcontroller, logic). avoid crossing digital tracks across analog tracks to reduce noise coupling and crosstalk. 5. reference inputs: it is recommended to use a minimum 10- f tantalum with a 0.1- f ceramic capacitor directly across the reference inputs, vrefp and vrefn. the reference input should be driven by a low- impedance source. for best performance, the reference should have less than 3- v rms in-band noise. for references with noise higher than this level, external reference filtering may be necessary. 6. analog inputs: the analog input pins must be driven differentially to achieve specified performance. a true differential driver or transformer (ac applications) can be used for this purpose. route the analog inputs tracks (ainp, ainn) as a pair from the buffer to the converter using short, direct tracks and away from digital tracks. a 1-nf to 10-nf capacitor should be used directly across the analog input pins, ainp and ainn. a low-k dielectric (such as cog or film type) should be used to maintain low thd. capacitors from each analog input to ground can be used. they should be no larger than 1/10 the size of the difference capacitor (typically 100 pf) to preserve the ac common-mode performance. 7. component placement: place the power supply, analog input, and reference input bypass capacitors as close as possible to the device pins. this layout is particularly important for small-value ceramic capacitors. larger (bulk) decoupling capacitors can be located farther from the device than the smaller ceramic capacitors. advance information 48 ads1278-sp sbas937 ? september 2018 www.ti.com product folder links: ads1278-sp submit documentation feedback copyright ? 2018, texas instruments incorporated 9.2.3 application curve figure 84 illustrates how the noise of the device, and thus, the snr, is determined by the mode that is utilized. figure 84. noise vs temperature 0 2 4 6 8 10 12 rms noise ( v) m -55 -35 -15 5 25 45 65 85 105 125 temperature (c) high resolution mode low power mode low speed mode high speed mode advance information 49 ads1278-sp www.ti.com sbas937 ? september 2018 product folder links: ads1278-sp submit documentation feedback copyright ? 2018, texas instruments incorporated 10 power supply recommendations the ads1278-sp has three power supplies: avdd, dvdd, and iovdd. avdd is the analog supply that powers the modulator, dvdd is the digital supply that powers the digital core, and iovdd is the digital i/o power supply. the iovdd and dvdd power supplies can be tied together if desired (1.8 v). to achieve rated performance, it is critical that the power supplies are bypassed with 0.1- f and 10- f capacitors placed as close as possible to the supply pins. a single 10- f ceramic capacitor may be substituted in place of the two capacitors. figure 85 shows the start-up sequence of the ads1278-sp. at power-on, bring up the dvdd supply first, followed by iovdd and then avdd. check the power-supply sequence for proper order, including the ramp rate of each supply. dvdd and iovdd may be sequenced at the same time if the supplies are tied together. each supply has an internal reset circuit whose outputs are summed together to generate a global power-on reset. after the supplies have exceeded the reset thresholds, 2 18 f clk cycles are counted before the converter initiates the conversion process. following the clk cycles, the data for 129 conversions are suppressed by the ads1278-sp to allow output of fully-settled data. in spi protocol, drdy is held high during this interval. in frame-sync protocol, dout is forced to zero. the power supplies should be applied before any analog or digital pin is driven. for consistent performance, assert sync after device power-on when data first appear. figure 85. start-up sequence drdy (spi protocol) dout (frame-sync protocol) internal reset clk 3v nom (1) avdd 1v nom (1) iovdd 1v nom (1) dvdd valid data 2 18 f clk 129 (max) t data advance information 50 ads1278-sp sbas937 ? september 2018 www.ti.com product folder links: ads1278-sp submit documentation feedback copyright ? 2018, texas instruments incorporated 11 layout 11.1 layout guidelines in any mixed-signal system design, the power-supply and grounding design plays a significant role. the device distinguishes between two different grounds: avss (analog ground) and dgnd (digital ground). in low frequency applications such as temperature sensing with thermocouples, laying out the printed circuit board (pcb) to use a single ground plane is adequate but care must be taken so that ground loops are avoided. ground loops act as loop antennas picking up interference currents which transform into voltage fluctuations. these fluctuations are effectively noise which can degrade system performance in high resolution applications. when placing components and routing over the ground plane, pay close attention to the path that ground currents will take. avoid having return currents for digital functions pass close to analog sensitive devices or traces. additionally, the proximity of digital devices to an analog signal chain has the potential to induce unwanted noise into the system. one primary source of noise is the switching noise from any digital circuitry such as the data output serializer or the microprocessor receiving the data. for the device, care must be taken to ensure that the interaction between the analog and digital supplies within the device is kept to a minimal amount. the extent of noise coupled and transmitted from the digital and analog sections depends on the effective inductances of each of the supply and ground connections. smaller effective inductances of the supply and ground pins results in better noise suppression. for this reason, multiple pins are used to connect to the digital ground. low inductance properties must be maintained throughout the design of the pcb layout by use of proper planes and layer thickness. to avoid noise coupling through supply pins, ti recommends to keep sensitive input pins away from the dvdd and dgnd planes. do not route the traces or vias connected to these pins across these planes; that is, avoid the digital power planes under the analog input pins. care should be taken to minimize inductance and route digital signals away from analog section. the analog inputs represent the most sensitive node of the adc as the total system accuracy depends on the how well the integrity of this signal is maintained. the analog differential inputs to the adc should be routed tightly coupled and symmetrical for common mode rejection. these inputs should be as short in length as possible to minimize exposure to potential sources of noise. advance information 51 ads1278-sp www.ti.com sbas937 ? september 2018 product folder links: ads1278-sp submit documentation feedback copyright ? 2018, texas instruments incorporated 11.2 layout example figure 86. ads1278-sp layout example advance information 52 ads1278-sp sbas937 ? september 2018 www.ti.com product folder links: ads1278-sp submit documentation feedback copyright ? 2018, texas instruments incorporated 12 device and documentation support 12.1 receiving notification of documentation updates to receive notification of documentation updates, navigate to the device product folder on ti.com. in the upper right corner, click on alert me to register and receive a weekly digest of any product information that has changed. for change details, review the revision history included in any revised document. 12.2 community resources the following links connect to ti community resources. linked contents are provided "as is" by the respective contributors. they do not constitute ti specifications and do not necessarily reflect ti's views; see ti's terms of use . ti e2e ? online community ti's engineer-to-engineer (e2e) community. created to foster collaboration among engineers. at e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. design support ti's design support quickly find helpful e2e forums along with design support tools and contact information for technical support. 12.3 trademarks e2e is a trademark of texas instruments. spi is a trademark of motorola, inc. all other trademarks are the property of their respective owners. 12.4 electrostatic discharge caution this integrated circuit can be damaged by esd. texas instruments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 12.5 glossary slyz022 ? ti glossary . this glossary lists and explains terms, acronyms, and definitions. advance information 53 ads1278-sp www.ti.com sbas937 ? september 2018 product folder links: ads1278-sp submit documentation feedback copyright ? 2018, texas instruments incorporated 13 mechanical, packaging, and orderable information the following pages include mechanical, packaging, and orderable information. this information is the most current data available for the designated devices. this data is subject to change without notice and revision of this document. for browser-based versions of this data sheet, refer to the left-hand navigation. advance information package option addendum www.ti.com 29-sep-2018 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples pads1278hfq/em active cfp hfq 84 1 tbd call ti call ti 25 to 25 pads1278hfq/em eval only (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) rohs: ti defines "rohs" to mean semiconductor products that are compliant with the current eu rohs requirements for all 10 rohs substances, including the requirement that rohs substance do not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, "rohs" products are suitable for use in specified lead-free processes. ti may reference these types of products as "pb-free". rohs exempt: ti defines "rohs exempt" to mean products that contain lead but are compliant with eu rohs pursuant to a specific eu rohs exemption. green: ti defines "green" to mean the content of chlorine (cl) and bromine (br) based flame retardants meet js709b low halogen requirements of <=1000ppm threshold. antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. other qualified versions of ads1278-sp : package option addendum www.ti.com 29-sep-2018 addendum-page 2 ? catalog: ads1278 ? enhanced product: ads1278-ep note: qualified version definitions: ? catalog - ti's standard catalog product ? enhanced product - supports defense, aerospace and medical applications important notice and disclaimer ti provides technical and reliability data (including datasheets), design resources (including reference designs), application or other design advice, web tools, safety information, and other resources ? as is ? and with all faults, and disclaims all warranties, express and implied, including without limitation any implied warranties of merchantability, fitness for a particular purpose or non-infringement of third party intellectual property rights. these resources are intended for skilled developers designing with ti products. you are solely responsible for (1) selecting the appropriate ti products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. these resources are subject to change without notice. ti grants you permission to use these resources only for development of an application that uses the ti products described in the resource. other reproduction and display of these resources is prohibited. no license is granted to any other ti intellectual property right or to any third party intellectual property right. ti disclaims responsibility for, and you will fully indemnify ti and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. ti ? s products are provided subject to ti ? s terms of sale ( www.ti.com/legal/termsofsale.html ) or other applicable terms available either on ti.com or provided in conjunction with such ti products. ti ? s provision of these resources does not expand or otherwise alter ti ? s applicable warranties or warranty disclaimers for ti products. mailing address: texas instruments, post office box 655303, dallas, texas 75265 copyright ? 2018, texas instruments incorporated |
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